Search...
ISA: LoongArch

LS2K0300 Specification

Processor core

64-bit dual-issue superscalar LA264 cores, based on LoongArch

Frequency

1GHz

High-speed cache

32KB L1 instruction cache and 32KB L1 data cache, Supports ECC; 512KB L2 shared cache, Supports ECC

Memory controller

16-bit DDR4-1600 controllers; supporting ECC

High-Speed I/O

2×USB 2.0, 2×GMAC, 1×LCD display

Other I/O

1 I2S, 4 CAN-FDs, 4 SPIs, 2 QSPIs, 2 eMMCs, 2 SDIOs, 1 LIO, 8-channel ADC, 4 I2Cs, 10 UARTs, 4 PWMs, 3 sets of TIMER, 106 GPIOs, RTC, HPET, JTAG, etc.

Packaging

12mm×12mm FC-CSP package with 286 pins

Power management

Supporting dynamic frequency scaling in processor core clock domains;supporting dynamic shutdown of the clocks of main modules

Typical power Consumption

<1W@1GHz

LS2K0300 Manual

LS2K0300 Application

m wap